1. Field of the Invention
The present invention relates to a semiconductor device which holds a high breakdown voltage when it is off and has a low resistance when it is on, and to a method of fabricating the same.
2. Description of the Background Art
FIG. 8 is a sectional view of a conventional diode having a PN junction. An N.sup.- epitaxial layer 2 is formed on an N.sup.+ substrate 1. A P.sup.+ layer 3 is formed on the N.sup.- epitaxial layer 2, for example, by ion implantation of boron. The N.sup.+ substrate 1 and the P.sup.+ layer 3 are provided with electrodes 8 and 7, respectively.
When voltage is applied to the diode having such a structure in the forward direction, that is, when a high potential is applied to the P.sup.+ layer 3 through the electrode 7 and a low potential is applied to the N.sup.+ substrate 1 through the electrode 8, the PN junction formed by the P.sup.+ layer 3 and the N.sup.- layer 2 is forward-biased and conducts.
When a low potential is applied to the P.sup.+ layer 3 and a high potential is applied to the N.sup.+ substrate 1, the PN junction is reverse-biased and a depletion layer extends. The depletion layer holds the applied voltage. The depletion layer hardly extends to the P.sup.+ layer 3 but to the N.sup.- layer 2 because of a difference in impurity concentration between the P.sup.+ layer 3 and the N.sup.- layer 2. The voltage capable of being held by the depletion layer is a breakdown voltage at the time that a reverse biased voltage is applied. In many cases, the diode is used in the state where the N.sup.- layer 2 is completely depleted, which state specifies a maximum breakdown voltage. This is because the undepleted N.sup.- layer 2 acts only as a resistor when it is biased in the forward direction and causes increase in resistance. As the impurity concentration of the N.sup.- layer 2 grows lower or as the thickness thereof grows larger, the breakdown voltage is increased.
For this reason, increase in the thickness of the N.sup.- layer 2 and decrease in the impurity concentration thereof are required in order to improve the breakdown voltage. However, there has been a problem that this accordingly provides increase in resistance at the time that the voltage is applied in the forward direction (hereinafter referred to as an "ON resistance").
Not only diodes but also transistors have such a problem.
FIG. 9 is a sectional view of a conventional VDMOS transistor. An N.sup.- epitaxial layer 2 is formed on an N.sup.+ substrate 1. P well regions 3 are formed by ion implantation of boron and the like. N.sup.+ source regions 4 are formed by ion implantation of arsenic and the like. On the N.sup.- layer 2 are provided gate oxide films 12, passivation films 5, gate electrodes 6 and a source electrode 7, in order. A drain electrode 8 is formed on the bottom surface of the N.sup.+ substrate 1.
The VDMOS having such a structure is an N channel type. When a low potential is applied to the source electrode 7 and the gate electrodes 6 and a high potential is applied to the drain electrode 8, no N-inversion occurs in the surfaces of the well regions 3 just under the gate electrodes 6. Similarly to the diode, the depletion layer extends from a PN junction formed by the well regions 3 and the N.sup.- layer 2 to the inside of the N.sup.- layer 2. Normally, the breakdown voltage is held, with the depletion layer extending through to the N.sup.+ substrate 1 (in an OFF-state). The depletion layer is formed practically within the N.sup.- layer 2 because of a difference in impurity concentration between the well regions 3 and the N.sup.- layer 2.
In this state, when a high potential is applied to the gate electrodes 6, the N-inversion occurs in the surfaces of the well regions 3 just under the gate electrodes 6. Electrons flow through the N-inverted portions of the well regions 3 to the N.sup.+ substrate 1, so that the VDMOS transistor is turned on.
The maximum breakdown voltage depends on the impurity concentrations and thicknesses of the N.sup.+ substrate 1, the N.sup.- layer 2 and the well regions 3. As the N.sup.- layer 2 in which the extending depletion layer holds the breakdown voltage is thicker and has a lower impurity concentration, the breakdown voltage is increased. The ON resistance mainly depends on the resistance of the N-inverted portions of the well regions 3 (hereinafter referred to as a "channel resistance"), a JFET resistance between the adjacent well regions 3 and the resistance of the N.sup.- layer 2. The channel resistance and the JFET resistance can be improved by processing technique, for example, by the formation of the thin well regions 3. The higher the impurity concentration of the N.sup.- layer 2 is, the smaller the resistance thereof is. The thicker the N.sup.- layer 2 is, the larger the resistance thereof is. In general, the resistance of the N.sup.- layer 2 accounts for the half of the whole resistance or more. The breakdown voltage and the ON resistance are in trade-off relation to each other.
Hence, there has been a problem that improvement in breakdown voltage is incompatible with reduction in ON resistance.